Basic ARM Cortex-M Structure

In this episode, let’s take a closer look at the ARM Cortex-M processors we entered earlier and examine their basic structures.

An ARM Cortex-M processor chip basically consists of an ARM-licensed Cortex-M core, peripherals added by chip manufacturers, and buses and bridges for communication between the core and these peripherals. Many examples such as serial communication units such as I2C, SPI, USART, digital-analog converter (DAC) or analog-digital converter (ADC) can be given to these peripheral units added by chip manufacturers. However, it should not be forgotten that the peripherals of chips produced by different manufacturers with the same architecture may differ from each other. Which peripherals will be found is entirely up to the chip manufacturer’s choice.

Simplified ARM Chip Block Diagram [1]

Basic ARM Cortex-M Chip Organization

ARM Cortex-M Chip

  • Memory
    • FLASH Memory: Instruction Memory (non-volatile)
    • SRAM/DRAM: Data Memory (volatile)
  • Processor Core
    • ALU (Arithmetic Logic Unit)
    • CPU (Central Process Unit)
    • NVIC (Interrupt Controller)
    • Instruction Fetch Unit
    • Instruction Decoder
    • Debug Interface
    • DSP (Digital Signal Processing)
    • FPU (Floating Point Unit)
    • Memory Interface
  • Buses
    • Data Bus
    • Instruction Bus
    • AHB (Advanced High Performance Bus)
    • APB (Advanced Peripheral Bus)
    • Bridges for connection between different busses
    • Bus matrix
  • GPIO
    • GPIO Ports (GPIO Port A, GPIO Port B,…)
  • Peripherals
    • I2C
    • SPI
    • USB
    • DAC
    • ADC
    • TIMER
    • OPAMP
    • LCD
  • DMA (Direct Memory Access)

The processor core communicates with FLASH, SRAM / DRAM, DMA and GPIO ports via a bus matrix. Bus matrix is an interconnection unit that provides a high communication bandwidth by allowing simultaneous data streams between units connected to it.

Peripheral units are connected to the bus matrix via bus bridges connecting AHB and APB. Generally AHB is used for high bandwidth communication and GPIO ports are connected to AHB. APB is for low-bandwidth communication. Many peripherals such as LCD, USART, I2C, SPI, OPAMP and timers are connected to the APB. AHB and APB are interconnected by bridges to fill the bandwidth gap between these two buses, buffering data and control signals and preventing data loss.

Each GPIO pin usually has more than one function. The function of a GPIO pin can be changed by software even during operation, but can only be used for one function at a time. In addition to being used as a pin digital input / digital output, it can also be used for more advanced and complex functions such as ADC, DAC, serial communication, timer functions. The GPIO functions of the chip may differ according to different chips as well as different chip manufacturers.

ALU (Arithmetic Logic Unit) is the unit that performs logical operations such as AND and integer arithmetic operations such as addition. ALU has two data inputs and one data output.

The CPU is the unit that generates control signals for internal digital circuits such as multiplexer selection signals, control signals of the ALU, and coordinates all components of the processor core.

The interrupt controller (NVIC) allows the processor core to stop the execution of the current task and immediately respond to special events or signals generated by software or peripherals.

The Instruction Fetch and Instruction Decoder units read a machine code from the command memory address pointed to by the program counter and analyze the command to determine what operations the processor core should perform. The CPU then generates the corresponding control signals depending on the decoding result.

The debug interface allows developers to use the host computer to start or stop software on a Cortex-M processor and monitor or modify processor registers, peripheral registers and memory in real time.

As I mentioned in my article where we know the Cortex-M processor family, Cortex-M4 cores have a DSP unit and can optionally have a single-precision FPU unit, but Cortex-M0 / M0 + / M1 / M3 cores do not have DSP and FPU support. Compared to Cortex-M4, FPU on Cortex-M7 cores can support both single-precision and double-precision operations.

The memory interface is responsible for accessing memory units such as SRAM / DRAM and FLASH.


  1. Microdigitaled. ARM Assembly Language Programming & Architecture
  2. Zhu, Y. (2018). Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C

Leave a Reply

Your email address will not be published. Required fields are marked *