ARM Cortex-M, I mentioned in the first post of the series, is a microprocessor family designed to have a low silicon mold size and very high energy efficiency. These processors typically have short pipelines and often have low maximum frequencies. Because they are designed to be very easy to use, they are very popular in the microcontroller and embedded systems market.
Cortex-M Core Family
The Cortex-M family is at the bottom of the performance spectrum. However, it is still more powerful than other processors designed for microcontrollers. While performance is very important, it is not the only criterion for microprocessor selection. For many applications, power consumption and cost are key to microprocessor selection. Cortex-M processor family includes many products for different needs.
Figure 1: Instruction sets in Cortex-M microprocessors (M0 – M7) 
Cortex-M0 has ARMv6-M architecture. It stands out for its very small silicone mold size and low power consumption. Besides almost all Thumb1 instructions and some Thumb2 instructions, It has a 3-stage pipeline.
Cortex-M0 + is an optimized superset of Cortex-M0. It is the most energy efficient option for small embedded systems. The pipeline has been reduced to 2 stages compared to Cortex-M0. The instruction set is the same as Cortex-M0.
Cortex-M1 has ARMv6-M architecture. It is specifically designed for use in FPGA chips. It has a 3-stage pipeline and the same instruction set as Cortex-M0.
Cortex-M3 has ARMv7-M architecture. It is very powerful for microcontroller applications with low power consumption with its rich instruction set. It has 3-stage pipeline with branch speculation. It contains all of the Thumb1 and Thumb2 instructions.
Cortex-M4 has ARMv7E-M architecture. In addition to all the features of the Cortex-M3, it includes Digital Signal Processing (DSP) instructions.
The Cortex-M7 is designed for high-end microcontrollers and process-intensive applications with almost twice the power efficiency of Cortex-M4. It has 6-stage pipeline with branch speculation, the longest pipeline of the family. It also has ARMv7E-M architecture.
Von Neumann & Harvard Architectures
There are two computer architectures. Von Neumann architecture in which data and commands are stored in the same memory and Harvard architecture in which they are stored in two physically separate memories. Although von Neumann architecture is cheaper, Harvard architecture is faster and consumes less energy.
Cortex-M0 / M0 + / M1 cores have Von Neumann architecture, while Cortex-M3 / M4 / M7 cores have Harvard architecture. However, the cores with Harvard architecture can be confused with Von Neumann due to their designs. This is because these cores actually have modified Harvard architectures.
For more detailed information, you can find my article on these two architectures here.
All of the Cortex-M cores contain most of the Thumb-1 instructions, some of the Thumb-2 instructions, and the 32-bit multiplication instructions. The higher model of the core, the more its features.
Cortex-M0 / M0 + / M1 contains the majority of Thumb-1 instructions and a small subset of the Thumb-2 instruction set (BL, DMB, DSB, ISB, MRS, MSR), apart from the (CBZ, CBNZ, IT) instructions added in the ARMv7-M architecture.
Cortex-M3 / M4 / M7 cores contain all instructions of Thumb-1 and Thumb-2 instruction sets. In Cortex-M3, hardware integer division and saturation arithmetic instructions have been added. In Cortex-M4, DSP instructions and optional single precision floating point unit (VFPv4-SP) have been added. In Cortex-M7, an optional double precision floating point unit (VFPv5) has been added.
Figure 4: ARM Cortex-M Instruction Variations (M0 – M7) 
Figure 5: ARM Cortex-M Instruction Groups (M0 – M7) 
- Yiu, J. (2016 & 2017). ARM® Cortex®-M for Beginners
- Wikipedia. ARM Architecture
- Wikipedia. ARM Cortex-M
- ARM Ltd. Website
- Wikipedia. Von Neumann Architecture
- Wikipedia. Harvard Architecture